Microprocessor systems are constructed to provide a variety of tasks and to this end are equipped with a bus via which various peripheral devices, which may be within the microprocessor chip or external thereto and which will be referred to herein as modules, can demand the attention of the data processor in the microprocessor system. The signal with which a module demands attention is commonly referred to as an interrupt request signal (or an `interrupt` for simplicity) since the external circuitry is asking the data processor to interrupt whatever it is currently doing in order to service more pressing external circuitry needs. The data processor services the interrupt by suspending whatever it is doing, executing a particular software program referred to as an interrupt handler, and then carrying on with its suspended operations. The key characteristic of an interrupt is that it is an unscheduled event, from the viewpoint of the data processor.
One prior art interrupt scheme is disclosed in U.S. Pat. No. 4,349,873, which is assigned to the assignee of the present invention and is hereby incorporated herein by reference. In system interrupts are presented to the data processor by means of an encoded value (which encodes a one-of-eight interrupt priority level) appearing on the three lines IPL0-IPL2. The data processor responds by executing an interrupt acknowledge bus cycle in order to retrieve from the interrupting module an interrupt vector (or an autovector indication). The disclosed data processor relies on externally provided hardware to perform arbitration between competing interrupting modules having the same interrupt priority level and to identify situations in which a false, or spurious, interrupt has been acknowledged.
A spurious interrupt occurs when the data processor executes an interrupt acknowledge cycle in response to an apparent interrupt request and no external circuitry responds with an interrupt vector or autovector indicator. Spurious interrupts can be caused, for example, by a noisy external environment. The data processor will stop and wait forever unless some kind of response is given to allow it to finish the interrupt acknowledge (IACK) cycle. In the system disclosed in the '873 patent, the data processor must be supplemented by external logic which identifies such situations and terminates the interrupt acknowledge cycle with a bus error (BERR) signal. Typically, such external logic simply waits for a predetermined length of time after the initiation of the interrupt acknowledge cycle before signalling a bus error. In many cases, this time-out period is the same as is used for all bus cycles to detect some error condition. During this time, no processing activity is occurring.